VLSI Architecture for Signal Speech and Image Processing 1st Edition by Durgesh Nandan, Basant Kumar Mohanty, Sanjeev Kumar, Rajeev Kumar Arya ISBN 9781774637302 1774637308

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Product details:
ISBN 10: 1774637308
ISBN 13: 9781774637302
Author: Durgesh Nandan, Basant Kumar Mohanty, Sanjeev Kumar, Rajeev Kumar

VLSI Architecture for Signal Speech and Image Processing 1st Edition Table of contents:

1. Evolution of 1-D, 2-D, and 3-D Lifting Discrete Wavelet Transform VLSI Architecture

1.1 Introduction

1.2 Types of Wavelets

1.2.1 1-Dimensional Architecture

1.2.2 2-Dimensional Architecture

1.2.3 3-Dimensional Architecture

1.3 Schemas for the Dwt Implementation

1.3.1 Lifting Scheme

1.3.2 Flipping Scheme

1.3.3 Convolution Scheme

1.4 Summary of the Architectures

1.5 Conclusion

References

2. Execution of Lifting-Scheme Discrete Wavelet Transform by Canonical Signed Digit Multiplier

2.1 Introduction

2.2 Lifting Scheme Discrete Wavelet Transform (Dwt)

2.3 Shift-Add Multip Lier

2.4 Multiplier Using Canonical Signed Digit

2.4.1 Characteristics of Csd Representation

2.5 Proposed Csd Multiplier

2.6 Synthesis Results

2.7 Conclusion

References

3. Radix-8 Booth Multiplier in Terms of Power and Area Efficient for Application in Field of 2D DWT Architecture

3.1 Introduction

3.2 Existing Booth Multiplier

3.2.1 Partial Products Structure

3.2.2 Booth Encoder (Be) and Selector Units

3.3 Proposed Booth Multiplier

3.3.1 Method Of Implementation

3.3.2 Partial Product Array (Ppa) Structure

3.3.3 Steps Involved

3.3.4 Theoretical Analysis Showing With An Example

3.4 Implementation of 2D Dwt Using Proposed Booth Multiplier Using Dwt

3.4.1 Implementation Of Existing 2D Dwt Architecture

3.4.2 Implementing 1D Dwt Architectures Using Proposed Booth Multiplier

3.5 Synthesis Results

3.6 Conclusion and Future Scope

References

4. Design and Performance Evaluation of Energy Efficient 8-Bit ALU at Ultra-Low Supply Voltages Using FinFET with 20 nm Technology

4.1 Introduction

4.2 Finfet Characteristics and Modeling

4.3 Proposed 8 Bit Alu Block Using Finfet Models

4.3.1 Gdi-Based Multiplexer

4.3.2 11T Full Adder

4.3.3 1-Bit and 8-Bit Alu

4.4 Simulation Results and Experimental Findings of the Proposed Work

4.5 Conclusion

References

5. Design and Statistical Analysis of Strong Arbiter PUFs for Device Authentication and Identification

5.1 Introduction

5.2 Background

5.2.1 Operation of Ring Oscillator PUF

5.2.2 Operation of Arbiter PUF

5.3 Architecture and Simulation

5.3.1 Proposed Mux-Decoder Based 16-Stage Arbiter PUF

5.3.2 PUF Security Metrics

5.4 Conclusion

References

6. An Impact of Aging on Arbiter Physical Unclonable Functions

6.1 Introduction

6.2 Metrics of PUF

6.2.1 Uniqueness

6.2.2 Reliability

6.2.3 Uniformity

6.3 Related Work

6.3.1 Effect of Temperature on Reliability of the PUF

6.3.2 Aging Mechanisms on Reliability of the PUF

6.3.3 Negative Bias Temperature Instability (NBTI)

6.3.4 Hot Carrier Injection (HCI)

6.3.5 Time-Dependent Dielectric Breakdown (TDDB)

6.3.6 Sources of Soft Errors in CMOS ICS

6.3.7 Radiation-Induced Soft Errors

6.3.8 Cross Talk Noise

6.3.9 Ground Bounce

6.4 Arbiter Pufs

6.4.1 Architecture and Operation of Arbiter PUFs

6.4.2 Mathematical Modeling of Arbiter PUF

6.4.3 Estimation of Aging on Arbiter PUFs

6.4.4 Aging Model for Arbiter Puf

6.4.5 Architecture of the Mux-Decoder PUF Architecture

6.4.6 Simulation Setup and Statistical Performance Analysis of Proposed PUF

6.5 Conclusion and Future Scope

References

7. Advanced Power Management Methodology for SoCs Using UPF

7.1 Introduction

7.2 Mathematical Modeling

7.2.1 Dynamic Power Dissipation

7.2.2 Signal Switching Power

7.2.3 Short Circuit Power

7.3 Static Power

7.4 Low Power Design

7.4.1 Clock Gating

7.4.2 Power Gating

7.4.3 Multi-Voltage Design

7.4.4 Voltage/Frequency Scaling

7.5 Need of Verification

7.6 Upf or Ieee 1801

7.7 UPF: Fundamental Modeling Constructs

7.8 Apb Description

7.8.1 Apb Protocol

7.9 APB Protocol Power Management Architecture

7.9.1 APB Implementation

7.9.2 Operating Modes

7.10 Simulation Results

7.11 Conclusion

Acknowledgment

References

8. Architecture Design: Network-on-Chip

8.1 Block of Data Format

8.2 Exchanging Methods

8.2.1 Circuit Exchanging

8.2.2 Block of Data Exchanging

8.2.3 Combinations of Different Exchanging

8.3 Asynchronous Fifo Implementation

8.3.1 Design of an Asynchronous Fifo Through Gray Code Counters

8.4 Gals Style of Communication

8.5 Wormhole Routing

8.6 Fundamental Channel (VC) Data Forwarding Device Architecture Design

8.7 Conclusion

References

9. Routing Strategy: Network-on-Chip Architectures

9.1 Packet Routing

9.2 Quality of Service (QoS)

9.3 Packet Flow Through a Typical Qos Policy

9.3.1 Qos Deployment Lifecycle

9.3.2 QoS Construction Workflow

9.3.3 Qos Configuration Workflow ((C))

9.3.4 QoS Tools

9.3.5 Classification and Marking

9.3.6 Queuing

9.3.7 Shaping and Policing

9.3.8 Wan Traffic Shaping

9.4 Congestion Control for Network on Chip

9.5 Flow Control in NOC

9.5.1 Flow Control

9.5.2 Circuit Switching

9.5.3 Flow Control

9.5.4 Data Unit

9.6 Router Design

9.6.1 Xy Routing Algorithm

9.6.2 Surrounding XY Routing

9.6.3 Oe Routing Algorithm

9.7 Designed NOC Links

9.7.1 Link Efficiency Mechanisms

9.8 Multicast Routing Schemes

9.8.1 Tree-Based Multicast

9.8.2 Path-Based Multicast

9.8.3 Path-Based Multicast Routing for 2D

9.8.4 Architecture of NOC

9.8.5 Design of NOC

9.8.6 Routing Algorithm for 2×2 Networks

9.8.7 Format Of Packet Formatting In 2D Routing

9.9 Fault-Tolerant Routing Algorithms

9.9.1 Routing and Reliable that is Adaptive Algorithms

9.10 Conclusion

References

10. Self-Driven Clock Gating Technique for Dynamic Power Reduction of High-Speed Complex Systems

10.1 Introduction

10.2 Related Work

10.3 Self-Driven Clock Gating

10.4 Methodology

10.5 Implementation of Clock Gating on 32-Bit Risc Processor

10.6 Simulation Results

10.7 Implementation

10.8 Results and Discussions

10.9 Conclusion

References

11. Optimization of SOC Sub-Circuits Using Mathematical Modeling

11.1 Introductory Note

11.2 System-On-Chip

11.3 Study of Device-Circuit Integration

11.3.1 Design Metrics

11.3.2 Analog and RF Metrics

11.4 Motivation

11.4.1 Scope of Work

11.4.2 Classical Optimization

11.4.3 Knowledge-Based Optimization

11.4.4 Global Optimization

11.4.5 Convex Optimization and Geometric Programming

11.4.6 Observations

11.5 Introduction To Geometric Programming

11.5.1 Standard Representation

11.5.2 Monomial And Posynomial Functions

11.5.3 Execution Process

11.5.4 Test of Feasibility, Trade-Off, and Sensitivity

11.5.5 Generalized Geometric Program

11.5.6 Software Package

11.5.7 Optimization Process Flow

11.6 Optimization of Biomedical Cmos Low-Noise Amplifier

11.6.1 Low-Noise Amplifier Topology

11.6.2 Formulation of Neural Recording Amplifier

11.6.3 Result Interpretation

11.6.4 Inferences

References

12. An Efficient Design of D Flip Flop in Quantum-Dot Cellular Automata (QCA) for Sequential Circuits

12.1 Introduction

12.2 QCA Majority Implementation

12.3 Quantum-Dot Cellular Automata Based Flip Flop Design

12.3.1 Jk Flip Flop

12.3.2 T Flip Flop

12.3.3 Sr Flip Flop

12.3.4 D Flip Flop

12.4 Shift Register Using D-Ff

12.5 Ring Counter Using D-Ff

12.6 Conclusion

References

13. Design and Performance Analysis of Controlled DC-DC Converter

13.1 Introduction

13.2 Digital Voltage Mode Control Of Dc-Dc Converter

13.3 Design And Modeling Of Dc-Dc Buck Converter

13.4 Digital Compensator

13.5 Pulse Width Modulation (PWM)

13.5.1 Analog Implementation of Pulse Width Modulation (PWM)

13.6 Digital Pulse Width Modulation (DPWM)

13.7 Simulation Results

13.7.1 Experimental Verification

13.8 Conclusion

References

Index

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Tags: Durgesh Nandan, Basant Kumar Mohanty, Sanjeev Kumar, Rajeev Kumar Arya, VLSI Architecture, Signal, Speech, Image Processing