Tunneling Field Effect Transistors Design Modeling and Applications 1st Edition by Arun Samuel, Young Suh Song, Shubham Tayal, Vimala, Shiromani Balmukund Rahi 1032348763 9781032348766

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ISBN 10: 1032348763

ISBN 13: 9781032348766

Author: T. S. Arun Samuel, Young Suh Song, Shubham Tayal, P. Vimala, Shiromani Balmukund Rahi

This book will give insight into emerging semiconductor devices from their applications in electronic circuits, which form the backbone of electronic equipment. It provides desired exposure to the ever-growing field of low-power electronic devices and their applications in nanoscale devices, memory design, and biosensing applications. Tunneling Field Effect Transistors: Design, Modeling and Applications brings researchers and engineers from various disciplines of the VLSI domain to together tackle the emerging challenges in the field of nanoelectronics and applications of advanced low-power devices. The book begins by discussing the challenges of conventional CMOS technology from the perspective of low-power applications, and it also reviews the basic science and developments of subthreshold swing technology and recent advancements in the field. The authors discuss the impact of semiconductor materials and architecture designs on TFET devices and the performance and usage of FET devices in various domains such as nanoelectronics, Memory Devices, and biosensing applications. They also cover a variety of FET devices, such as MOSFETs and TFETs, with various structures based on the tunneling transport phenomenon. The contents of the book have been designed and arranged in such a way that Electrical Engineering students, researchers in the field of nanodevices and device-circuit codesign, as well as industry professionals working in the domain of semiconductor devices, will find the material useful and easy to follow.

Tunneling Field Effect Transistors Design Modeling and Applications 1st Table of contents:

Chapter 1 Challenges of Conventional CMOS Technology in Perspective of Low-Power Applications

1.1 Introduction

1.2 CMOS Inverter Design

1.3 Scaling of Transistors and Second-Order Effects

1.3.1 Threshold Voltage Reduction

1.3.2 Subthreshold Swing

1.3.3 Subthreshold Leakage Current

1.3.4 Gate Leakage Power

1.3.5 Band-to-Band Tunneling Leakage

1.4 Summary

References

Chapter 2 Basic Science and Development of Subthreshold Swing Technology

2.1 Introduction

2.2 Subthreshold Behavior

2.3 Parameters of Subthreshold Swing

2.4 A Survey Analysis of Subthreshold Swing

2.4.1 Gate Material

2.4.2 Effect of Temperature

2.4.3 Effect of Scale Length

2.5 Conclusion

References

Chapter 3 Historical Development of MOS Technology to Tunnel FETs

3.1 Introduction

3.2 MOSFETs Scaling

3.3 Short Channel Effects (SCEs)

3.3.1 Subthreshold Current

3.3.2 Threshold Voltage Roll-Off

3.3.3 Drain Induced Barrier Lowering (DIBL)

3.3.4 Hot Carrier Effects

3.3.5 Gate-Induced Drain Leakage Current (GIDL)

3.3.6 Velocity Saturation

3.4 Trade-Off in the Device Design

3.5 SOI-Based MOSFETs

3.6 Multigate and FinFETs

3.7 Tunnel FETs

3.8 The Importance of Tunnel FETs

3.9 Tunnel FETs Evolution

3.10 TFETs Device Operation

3.11 Challenges in Tunnel FETs

3.12 Gate-All-Around-Tunnel FETs

3.13 Vertical Tunnel FETs

3.14 2D- Material-Based TFETs

3.14.1 Basics of 2D-Materials

3.14.2 Transistor Characteristics of 2D-Materials

3.14.3 Reliability of 2D Material-Based Transistors

3.14.4 TFETs Based on the 2D Materials

3.15 Summary

References

Chapter 4 Modeling and Simulation of Dual Material Double Gate Tunnel FETs

4.1 Introduction

4.2 Dual Material Gate TFET

4.3 DMG TFET Characteristics

4.4 DMG TFET Drain Current Modeling

4.5 Development of the Surface Potential Model

4.6 Drain Current Model

4.7 Conclusion

References

Chapter 5 Modeling of Gate Engineered TFET: Challenges and Opportunities

5.1 Introduction

5.2 Device Structure

5.3 Analytical Modeling of Single Gate SOI TFETs

5.3.1 Modeling of Surface Potential

5.3.2 Electric Field of SG SOI TFET

5.3.3 Drain Current of SG SOI TFET

5.4 DMG TFET-Analytical Formulation

5.4.1 Device Schematic of Dual Material Gate TFET

5.5 Analytical Modeling of Dual Material Double Gate Tunnel Field Effect Transistor

5.5.1 Introduction

5.5.2 Device Structure of DMDG TFET

5.6 Surrounding Gate TFET- Analytical Formulation

5.6.1 Device Schematic of Surrounding Gate Tunnel FET

5.6.2 Modeling of Surface Potential

5.6.3 Modelling of Electric Field

5.6.4 Derivation of Drain Current

5.7 Summary

References

Chapter 6 Evolution of Heterojunction Tunnel Field Effect Transistor and its Advantages

6.1 Introduction

6.2 Double Gate Homojunction TFET

6.3 Heterojunction TFET

6.3.1 Germanium Heterojunction DGTFET

6.3.2 Germanium Heterojunction DGTFET

6.3.3 Gallium Arsenide Heterojunction DG TFET

6.3.4 Heterojunction GaN/InN/GaN DG-TFET

6.4 Nanowire Tunnel Field Effect Transistor

6.5 Gate All Around (GAA) Heterojunction TFET

6.5.1 Germanium/Silicon GAA Heterojunction (HJ) TFET

6.5.2 GaSb/InAs Heterojunction Gate All Around Tunnel FET

6.5.3 Ge/GaAs-Based Heterojunction Gate-All-Around (GAA) Tunneling Field-Effect Transistor (TFET)

6.5.4 GaAs0.5Sb0.5/In0.53Ga0.47As Heterojunction GAA TFET

6.6 Gate Engineering Heterojunction TFET

6.6.1 Dual Material (DM) Elliptical Gate All Around (GAA) Heterojunction TFET

6.6.2 Triple Material (TM) Ge/Si Gate All Around(GAA) Heterojunction TFET

References

Chapter 7 Analog/RF Performance Analysis of TFET Device

7.1 Introduction

7.2 Analog Parameters

7.2.1 The Transconductance (gm)

7.2.2 The Transconductance Generation Factor (TGF)

7.2.3 Drain Current

7.2.4 Surface Potential

7.2.5 Electric Field

7.2.6 Tunnel Path

7.3 RF Parameters

7.3.1 Cut-off Frequency (fT)

7.3.2 Gate-to-Drain Capacitance (CGD)

7.3.3 Gate-to-Source Capacitance (CGS)

7.3.4 Gain Band-Width Product (GBW)

7.3.5 Frequency of Oscillation (fmax)

7.3.6 Intrinsic Gate Delay (τint)

7.3.7 Transit Time (τ)

7.4 Investigation of Analog/RF Performance of Gate-All-Around (GAA) TFET

7.4.1 Drain Current (ID)

7.4.2 Electric Field Profile

7.4.3 Transconductance (gm)

7.4.4 Gate Source Capacitance (CGS) and Gate Drain Capacitance (CGD)

7.4.5 Cut-off Frequency (fT)

7.4.6 Gain-Bandwidth Product (GBP)

7.4.7 Transit Time (τ)

7.5 Investigation of Dielectric Pockets (DP) Influence in TFET

7.5.1 Drain Current (ID)

7.5.2 Electric Field

7.5.3 Transconductance (gm)

7.5.4 Gate-Drain Capacitance (CGD) and Gate-Source Capacitance (CGS)

7.5.5 Cut-off Frequency (fT)

7.5.6 Gain-Bandwidth Product (GBP)

7.5.7 Transit Time (τ)

7.6 Conclusion

References

Chapter 8 DC Analysis and Analog/HF Performances of GAA-TFET with Dielectric Pocket

8.1 Introduction

8.2 Structure of the Device and Simulation Set-up

8.3 Fabrication Possibility

8.4 Simulation Results and Discussion

8.4.1 Optimization of Dielectric Constant (k) of DP

8.4.2 Impact of Varying Length of DP

8.4.3 Effect of Varying Thickness of DP

8.5 Conclusion

References

Chapter 9 Investigation on Ambipolar Current Suppression in Tunnel FETs

9.1 Introduction

9.2 Working Mechanism

9.3 Ambipolar I-V Characteristics of TFET

9.4 Common IAMB Reduction Techniques

9.4.1 Gate-drain Underlap

9.4.2 Reduced Drain Doping Concentration

9.4.3 Use of Low-k Spacer

9.4.4 Influence of the Contact Layout

9.5 Ambipolarity in Homojunction TFET

9.5.1 Structural Engineering

9.5.2 Doping Engineering

9.5.3 Junction-less/Doping-less Design

9.6 Ambipolarity in Heterojunction TFET

9.6.1 Si/GaAs TFET

9.6.2 Si/GaAs Doping-less TFET

9.6.3 Pseudo Split Gate In0.53Ga0.47As/InP Heterojunction Tunnel FET

9.7 Ambipolar Suppression in Advanced TFET

9.7.1 Z-shaped TFET

9.7.2 Dual-MOS TFET

9.7.3 Recessed-gate TFET

9.7.4 Electron-Hole Bilayer TFET

9.8 Summary

References

Chapter 10 Analysis of Channel Doping Variation on Transfer Characteristics to High-Frequency Performance of F-TFET

10.1 Introduction

10.2 Simulated Device Structure and Parameters

10.3 DC Characteristics

10.4 Analysis of Analog/RF FOMs

10.5 Conclusion

References

Chapter 11 Design of Nanotube TFET Biosensor

11.1 Introduction

11.2 Biosensor Structure, Dimensions, and Simulation Setup

11.3 Result and Discussion

11.3.1 Basic Electrical Characteristics of the Biosensor

11.3.2 Sensitivity Analysis by DC Parameters

11.3.3 High-frequency Parameters Analysis of Neutrally Charged and Charged Biomolecules

11.3.4 Sensitivity Analysis by High-Frequency Parameters

11.3.5 Optimization

11.4 Conclusion

References

Chapter 12 TFET-based Memory Cell Design with Top-Down Approach

12.1 Introduction: Demand for Low Power Devices

12.2 Flow Chart for Explaining TFET-based Memory Device

12.3 Basic Structure of Memory Cell: SONOS Structure

12.4 Operation Principle of SONOS Memory Structure: Program/Erase/Read

12.5 Utilizing TFET for Memory Device: TFET-based Memory for Low Power Application

12.6 Additional Advantage of TFET-based Memory Device: Fast Erase Speed

12.7 Future of TFET-based Memory Cell Design: Opportunities & Challenges

12.8 Conclusion

Acknowledgments

References

Chapter 13 Designing of Nonvolatile Memories Utilizing Tunnel Field Effect Transistor

13.1 Introduction

13.2 Workflow and Scope

13.2.1 Workflow

13.2.2 Scope

13.3 Roadmap for Future Memory Technology for Low Power Operation

13.4 Basic Design Goals in Future Memory Design

13.5 Basic Structure of Memory Cell

13.6 Physical Principle of Memory Cell: Program/Erase/Read Operation

13.6.1 Read Operation

13.6.2 Write Operation

13.7 Design Optimization with Steep Subthreshold Swing Transistor

13.7.1 Forward p-i-n Current

13.7.2 Low Current of TFET

13.8 Conclusion

References

Chapter 14 TFET-based Universal Filter for Low-Power Applications

14.1 Introduction

14.2 Overview of TFET

14.3 Performance Investigation of DO-CCII

14.4 DO-CCII-based Universal Biquadratic Filter

14.5 Conclusion

References

Chapter 15 TFET-based Level Shifter Circuits for Low-Power Applications

15.1 Introduction

15.1.1 Motivation

15.1.2 TFET Overview

15.1.3 Working of TFET

15.2 Literature Review

15.2.1 Literature Review

15.3 Level Shifter Circuits

15.3.1 Level Shifter

15.3.2 Measurement of Performance Metrics of Level Shifter

15.4 Circuit Topologies of Level Shifters

15.4.1 Cross Coupled Level Shifter

15.4.2 Current Mirror Level Shifter (CMLS)

15.4.3 TFET-based Wilson Current Mirror Level Shifter (WCMLS)

15.4.4 TFET-based Implementation of Existing Level Shifter

15.5 Results and Discussion

15.5.1 Device Parameters and Simulation Conditions

15.5.2 Frequency of Operation

15.5.3 Level Shifting Range

15.5.4 Power Dissipation of Voltage Level Shifter

15.5.5 Delay of TFET-based Voltage Level Shifter

15.5.6 PDP of TFET-based Voltage Level Shifters

15.6 Importance of Performance Metrics of Level Shifters

15.7 Conclusion

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Arun Samuel, Young Suh Song, Shubham Tayal, Vimala, Shiromani Balmukund Rahi